In the art of fabricating integrated circuit packages, the continuing goals are to make the circuit and the associated package smaller, more dense, more thermally efficient, and lower cost. Numerous packaging methodologies have been proposed to address these and other areas of concern. The increasing number of integrated circuit pads correspondingly increases the size of the packages and adds to the cost of the end product. Because the size of the package is an exponential function of the number of leads emanating from the die, increasing density rapidly and dramatically increases 1;he package size. One of the approaches to this problem has been to place multiple die on a single substrate, and then provide the die-to-die interconnections on the substrate. This technology is known as tile multichip module.
Multichip modules containing eraseable programmable read-only memory (hereinafter called EPROM) die which can be erased by an ultraviolet (UV) light rays consist of one or more EPROM chips mounted on a common substrate. Packaging the multichip module creates significant problems with EPROM die. The multichip module and the chips are covered with a cap to physically protect them from deleterious effects of the environment. The cap may be made entirely from a UV light transmitting material, but is typically made from a UV opaque material, such as ceramic, metal, or plastic. Regardless of the material used, the cap must be capable of transmitting UV light to the EPROM. Because of these complex and costly covers, conventional multichip EPROM packages suffer from a number of disadvantages, such as:
(1) UV light permeable resins are rather expensive, and even though they provide sufficient UV transmittance, it would be desirable to eliminate them. PA1 (2) The difference in thermal expansion coefficients between the base material, the cover, and the UV light permeable resin sometimes generates cracks in the package. PA1 (3) The complex covers are relatively heavy and bulky, thereby restricting the packaging density on a printed circuit board. PA1 (4) Assembly requires substantial time. PA1 (5) Cracks can be formed in the package because ceramic covers are quite fragile with regard to shock. PA1 (6) The need to add a separate cover and UV window to the cover creates a finished assembly which is larger than desired. A package with less wasted space in the vertical direction would be desirable. PA1 (7) The complex covers are expensive, thereby increasing the cost of the finished package.
Thus, a continuing goal in the integrated circuits art is a package design that addresses these problems satisfactorily in an arrangement that can be reliably manufactured at a low cost. Such a package has not previously been in existence for multichip EPROM modules.